The Shift Register

Unit 6

Sequential logic: Characteristics,Flip-flops,Clocked RS,D type, JK,T type and Master slave Flip-flops,State table,State diagram and state equation,flip-flop excitation table

The Shift Register

The Shift Register is another type of sequential logic circuit that can be used
for the storage or the transfer of data in the form of binary numbers. This
sequential device loads the data present on its inputs and then moves or
“shifts” it to its output once every clock cycle, hence the name “shift register”.
A shift register basically consists of several single bit “D-Type Data Latches”,
one for each data bit, either a logic “0” or a “1”, connected together in a serial
type daisy-chain arrangement so that the output from one data latch becomes
the input of the next latch and so on.
The number of individual data latches required to make up a single Shift
Register device is usually determined by the number of bits to be stored.
Shift Registers are used for data storage or for the movement of data and are
therefore commonly used inside calculators or computers to store data such as
two binary numbers before they are added together, or to convert the data
from either a serial to parallel or parallel to serial format.
Shift register IC’s are generally provided with a clear or reset connection so
that they can be “SET” or “RESET” as required. Generally, shift registers
operate in one of four different modes with the basic movement of data
through a shift register being:
 Serial-In to Parallel-Out (SIPO) - The register is loaded with serial
data, one bit at a time, with the stored data being available at the output in
parallel form.
 Serial-In to Serial-Out (SISO) - The data is shifted serially “IN” and
“OUT” of the register, one bit at a time in either a left or right direction
under clock control.
 Parallel-In to Serial-out (PISO) - The parallel data is loaded into the
register simultaneously and is shifted out of the register serially one bit at
a time under clock control.
 Parallel-In to Parallel-Out (PIPO) - The parallel data is loaded
simultaneously into the register, and transferred together to their
respective outputs by the same clock pulse.